1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device. More particularly, the present invention relates to a fabrication method for a low dielectric insulation structure comprising an air-gap.
2. Description of the Related Art
Advances in the semiconductor technology continuously decrease the semiconductor device dimension into the deep sub-micron territory. As the density of an integrated circuitry increases, the wafer surface becomes insufficient for the manufacturing of the necessary numbers of interconnects. To accommodate the increased number of interconnects, the multi-level metal conductive connect design becomes the approach for the Very Large Scale Integration technology.
The continuous decrease in the distance between the metal conductive layers, however, is accompanied by an increase in the aspect ratio of the dielectric layer between the metal conductive layers. The coupling capacitance between the metal conductive layers is thereby increased leading to the formation of a parasitic capacitance.
The parasitic capacitance in a microelectronic device contributes to the effect such as an increase of the RC delay time when electronic signals are being transmitted between the metal linings. As a result, the speed of the electronic signal transmission between the metal linings is retarded and the operational speed of the semiconductor device is limited.
In order to reduce the RC time delay on signal transmissions, currently copper metal (with an electrical resistivity of approximately 1.7 microohm-cm) has been employed to replace the aluminum metal (with an electrical resistivity of approximately 2.7 microohm-cm) as conductive linings for the connect system to lower the resistance of the metal conductive linings. According to the formula of "C=.epsilon.(A/d)", lowering the parasitic capacitance by altering the geometric parameters such as the conductive lining area A and the thickness d of the dielectric layer between two electrodes of the equivalent capacitor are another two approaches to reduce the RC time delay. However, the geometric approach is not a feasible approach due to limitations of the process condition and the conductive resistance. The research on low dielectric constant .epsilon.materials, as a result, has become a major developmental trend in the semiconductor industry.
The inter metal dielectric (IMD) layer for use in between the metal conductive linings, in general, requires to have properties such as high reliability, high mechanical strength, easy manufacturing, non-hygroscopic and easy to incorporate with the metal conductive linings. Currently, materials with a low dielectric constant that are being developed are mainly the spin on polymer (SOP) and the organic spin on glass (OSOG) with a dielectric constant of approximately between 2 to 4. The structure of the SOP and OSOG types of dielectric material, however, is slightly loose, and the mechanical strength of these materials is less favorable, comparing to the silicon oxide material. Furthermore, these newly developed dielectric materials are hygroscopic. The penetration of water vapor into the dielectric layer, which further leads to the occurrence of out-gassing during the subsequent formation of the metal plug and a poison phenomenon, is resulted.
As the manufacturing of semiconductors enters the deep sub-micron territory, the dielectric layer requires an even lower dielectric constant to accommodate the diminishment of the device dimension and to improve the performance of the device. Air, having a dielectric constant close to one and being inexpensive, has become one of the dielectric materials currently under development. If air can be used as a dielectric material, the insulation effect can be highly increased.